Fairchild Semiconductor fdg6320c free download

File name fdg6320c.pdf

November 1998 FDG6320C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V, field effect transistors are produced using Fairchild's RDS(ON) = 5.0 @ VGS= 2.7 V. proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize P-Ch -0.14 A, -25V, RDS(ON) = 10 @ VGS= -4.5V, on-state resistance. This device has been designed RDS(ON) = 13 @ VGS= -2.7V. especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since Very small package outline SC70-6. bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias Very low level gate drive requirements allowing direct resistor values. operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). SC70-6 SOT-23 SuperSOTTM-6 SOT-8 SO-8 SOIC-14 S2 1 6 G2 D1 .20 2 5 D2 pin 1 G1 3 4 SC70-6 S1 Absolute Maximum Ratings TA = 25oC unless other wise noted Symbol Parameter N-Channel P-Channel Units VDSS Drain-Source Voltage 25 -25 V VGSS Gate-Source Voltage 8 -8 V ID Drain